Integrated circuits are generally fabricated on a thin silicon wafer or substrate. Semiconductor devices and electrical interconnections that form the integrated circuit are conventionally made by building many mask layers on top of one another on the substrate. Each successive mask layer may have a pattern that is defined using a mask. A mask has a shape used for patterning features in a particular process step during fabrication. The mask layers are fabricated through a sequence of pattern definition steps using the masks, which are interspersed with other process steps such as oxidation, etching, doping and material deposition. When a mask layer is defined using a mask chosen or provided by a customer, the mask layer is programmed or customized.
The lowest, “base” layers of an integrated circuit include the active areas of the semiconductor devices, such as diffusion regions and gate oxide areas, and desired patterns of the poly-silicon gate electrodes. One or more metal and insulating layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment of one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
Several types of integrated circuits have been developed which have modules or blocks of transistors that are partly fixed and partly programmable and/or customizable. The utility of these modular chips is determined by factors such as complexity, cost, time, and design constraints to create functional electronics from these generic blocks of transistors. Field Programmable Gate Array (FPGA) refers to a type of logic chip in which all mask layers are pre-fabricated by an Application Specific Integrated Circuit (ASIC) vendor and has a function that may be easily reprogrammed in the field with trivial modifications. FPGAs, however, are very large and have relatively high cost per function, relatively low speed, and high power consumption. An ASIC is an integrated circuit designed specifically for a particular application or use. In a fully programmable ASIC, all mask layers are programmed or customized by the logic designer. A typical example of a fully programmable ASIC is a cell-based ASIC (CBIC). While a fully programmable ASIC efficiently uses power and area as compared to FPGAs, it is very complex to design and prototype. In a semi-programmable ASIC, some, but not all, mask layers are programmable. For example, some or all of the base layers may be pre-fabricated by the ASIC vendor, and the remaining layers, such as the metal layers, may be programmed by the logic designer to interconnect the semiconductor elements to perform the desired function. A typical example of a semi-programmable ASIC is a gate-array-based ASIC. A semi-programmable ASIC may combine the high-density, high-performance benefits of standard-cell ASICs with the fast time-to-market and customization benefits of FPGAs.
Accordingly, semi-programmable ASICs have recently become more popular. Integrated circuit foundries have begun to develop standard, or base, platforms, known as “slices” containing the base layers of an integrated circuit but without the metal interconnection layers. The base layers are patterned to form gates that may be configured into cells using tools supplied by the foundry. The chip designer designs additional metal layers for the base platform to thereby configure the integrated circuit into a custom ASIC employing the customer's intellectual property (IP). An example of such configurable base platform is the RapidChip® (RC) platform available from LSI Logic Corporation of Milpitas, Calif. The RapidChip® platform permits the development of complex, high-density ASICs in minimal time with significantly reduced design and manufacturing risks and costs.
The design effort for a semi-programmable ASIC encompasses several stages. After the chip size has been selected and the input-output (I/O) cells have been placed in a layout pattern for the base platform, megacells, including memories and other large hard macros (hardmacs), are placed. Thereafter, standard cells are placed to complete the chip design.
Rapidly increasing mask costs and lengthening ASIC design cycles necessitate new solutions to produce custom logic devices on time and on budget. As fewer companies can make a business case for cell-based ASIC designs, they revert to less-costly options or try to replace custom logic devices with off-the-shelf Application Specific Standard Products (ASSP). FPGAs offer an alternative, but they come with significant drawbacks including limited performance and capacity, high unit costs and high power consumption.
This dilemma has caused a resurgence of gate-array style devices that are now being marketed as Structured ASICs, in an attempt to address the shortcomings of standard cell ASICs. On a system level, one way to achieve high integration efficiency and performance while providing flexibility is to combine discrete ASICs and FPGAs on a printed circuit board. Embedded FPGA technology may enable the combination of the flexibility and time-to-market of FPGAs with the capacity and performance of an ASIC.
Advanced 90 nm and 65 nm technology may make things worse again. While the mask charges may continue to increase and design time and tooling costs may spin out of control, every process node may make FPGA-based products more attractive. On the other hand, technology limits such as power consumption may make FPGA type devices much more complicated to develop and to integrate on the system level. Thus, both ASIC and FPGA type of devices may not serve the markets of the future.
The embedded FPGA technology may be a solution to address the foregoing-described problem. Conventionally developers of embedded FPGAs concentrate on a fixed technology driven embedded FPGA solution. However, the integration of such an embedded FPGA into System-on-Chip (SoC) designs may be difficult, ASIC design flows may be broken, and the flexibility on the SoC system level may be not addressed.
Thus, it would be desirable to provide a system and method which may effectively address the foregoing-described problems.